In an asynchronous interface circuit for transferring data between asynchronous circuits, clock transfer is performed. This transfer is performed by receiving data from a source circuit in synchronism with a clock signal in the source circuit and by outputting the data to a destination circuit in synchronism with a clock signal in the destination circuit.
A clock transfer circuit therefore may apply a data transfer method to an asynchronous buffer without synchronization between a source (or transmitter) and a destination (or receiver). For example, the asynchronous buffer may be a clock transfer circuit including a first-in-first-out buffer (hereinafter called FIFO) between a data transmission path of a transmitter and a data transmission path of a receiver. The data written within the FIFO in synchronism with the write clocks transmitted from a transmitter may be read in the order of writing in synchronism with read clocks in a receiver.
Asynchronous interface circuits may have predetermined interface specifications because the manufacturers of the source and destination of data may often differ. For example, ONFI (Open NAND Flash Interface) specifications that are interface specifications for NAND-type flash memories define a flash memory interface based on a DDR (Double Data Rate) interface. According to the ONFI specifications, in response to a data read request from a controller, a flash memory generates an output clock signal including the equal number of clocks to the number of clocks for outputting the requested data and outputs the data in synchronism with the output clock signals. The details of the interface specifications are defined by ONFI that is one of the industry standard groups, and the specifications are published (URL;http://onfi.org/). Then, there is Japanese Laid-open Patent Publication No. 7-115410 as a reference document.
However, even on the basis of the specifications, normal data transfer may sometimes be difficult in such asynchronous interface circuits in the past.
For example, the ONFI specifications are based on a DDR interface, but a target flash memory may not typically be equivalent to a general DDR-RAM (Random Access Memory) for internal operations. For that reason, even when a control device (hereinafter called controller) that controls reading and writing data from and to a flash memory is designed on the basis of the ONFI specifications, the controller may not be allowed to connect to all flash memories designed on the basis of the ONFI specifications. The examples will be described below.
FIG. 6 illustrates a timing example for reading DDR-data on the basis of the ONFI specifications. Reading DDR-data is data transfer from a flash memory to the controller.
The illustrated CLK is a clock signal to be generated by the controller in a destination, and the clock cycle is 12 nanoseconds (hereinafter called nsec), for example. The ALE (address latch enable)/CLE (command latch enable) is a signal to be generated by the controller and is asserted during the period for the number of clock cycles according to the number of data to be read from the flash memory. In the example in FIG. 6, since data for five words are to be read, the ALE/CLE has High level during a period of five clock cycles of the clock CLK. The period will be called assert cycle hereinafter.
The flash memory counts the clocks CLK during the assert cycle of the ALE/CLE, and determines the number of DQS clocks to be issued. The DQS is an output clock signal for transferring output data (which is read data from the controller). In the illustrated example, the number of clocks CLK detected during an assert cycle 90 of the ALE/CLE is “5”, and the number of DQS clocks to be issued is thus “5”. However, a delay tDQSD 91 occurs during the period from the detection by the flash memory of the clock signal CLK from the controller to the actual issuance of the DQS. The ONFI specifications define that the maximum value of the delay tDQSD 91 is 20 nsec. Since flash memories have individual differences, the delay tDQSD 91 is allowed a margin of 0 to 20 nsec. The value is higher than the clock cycle (12 nsec) on the controller, and it is difficult to define the timing for capturing data on the controller. This causes a problem that the controller may not capture the data in a timed manner.
The data transfer using a FIFO includes data transmission in at least two stages of capturing data (DQ) and writing the data to the FIFO. The number of DQS clocks to be issued corresponds to the size of the data requested by the controller. Thus, when the controller transmits read data in the two or more stages in synchronism with the DQS, it is difficult to transfer the last data 92. In other words, the last data 92 are captured in synchronism with the last DQS clock (in the first stage). However, since no DQS occurs, the processing in the second stage in which the last data are to be written to the FIFO is not performed.